1. Field of the Invention
The present invention relates to a thin-film transistor (TFT) and a method for manufacturing the same, and more particularly, to a TFT having a lightly doped drain (LDD) and an offset structure for suppressing the leakage current and a method for manufacturing the same.
2. Description of the Prior Art
Generally, a thin-film transistor (TFT) is used as a switching device in an active matrix liquid crystal device (LCD) for controlling the operation of each pixel. Further, a TFT can be applied to a semiconductor memory device or an image sensor.
To manufacture the TFT, which is used as a switching device, polysilicon, amorphous silicon, etc. have been used as the main material. A polysilicon TFT has a field effect mobility of 10-200 cm.sup.2 /V.s which is far greater than that of 1 cm.sup.2 /V.s of an amorphous silicon TFT. Thus, the polysilicon TFT has an advantage in that it has a higher on-current handling capability so that it is widely used in a high-density display device having a large capacitance or a memory device.
In the meantime, when manufacturing a polysilicon TFT for a liquid display device, a cheap glass substrate should be used to lower the manufacturing cost, as in the case of manufacturing an amorphous silicon TFT. Therefore, the process for manufacturing the polysilicon TFT should be performed at a limited temperature (below about 600.degree. C.) due to the thermal characteristics of the glass substrate. Further, an annealing process, after performing an ion-implantation into a silicon layer for forming the source and drain regions of a transistor, cannot be performed at a sufficiently high temperature due to the limited temperature. Therefore, the crystalline characteristics of the silicon layer is not sufficiently recovered. A TFT obtained in accordance with the above process at a low temperature has a high leakage current at a reverse biased voltage and a signal delay due to the resistance of the used material which are not found in a TFT obtained by a high temperature annealing process. Carriers trapped in the defects inside the active region are moved to a drain region by an electric field applied between a gate electrode and a drain region to generate leakage current.
To prevent such a leakage current, in a conventional metal oxide semiconductor (MOS) device, a method has been suggested for weakening the electric field applied between the gate electrode and a drain region. For example, an LDD-structured device or an offset-structured device has been suggested for this purpose.
FIG. 1 is a sectional view for illustrating a conventional LDD-structured MOS TFT.
Referring to FIG. 1, a conventional LDD-structured NMOS TFT will be explained hereinafter. On an insulating substrate 10, a polysilicon layer 12 is formed, which comprises n.sup.+ source and drain regions 12a wherein an n-type impurity has been highly doped, a channel region 12b between source and drain regions 12a, and an n-LDD region 12c between source and drain regions 12a and channel region 12b wherein n-type impurities have been lightly doped. On polysilicon layer 12, which comprises source and drain regions 12a, channel region 12b and LDD region 12c, a gate insulating layer 14 is formed and a gate electrode 15 comprising an impurity-doped polysilicon is formed on a portion of the gate insulating layer 14 over channel region 12b. Silicon thermal oxide layer 16 covering the upper and sidewall surfaces of gate electrode 15 is formed over LDD region 12c. Source and drain regions 12a and gate electrode 15 make up an NMOS LDD-structured TFT. An insulating interlayer 17 is formed on the structure having the above TFT for electrically isolating the TFT from a conductive layer which is formed in a subsequent step. Metal wirings 18 connected to source and drain regions 12a and gate electrode 15 are formed on insulating interlayer 17 for operating the above-described TFT.
The above-described NMOS LDD-structured TFT is manufactured as follows. At first, the thin polysilicon layer 12 is formed on the insulating substrate 10. On polysilicon layer 12, gate insulating layer 14 is formed by depositing an insulating material such as silicon oxide or by thermally oxidizing the upper surface portion of the polysilicon layer. Then, a material for forming a gate electrode, such as impurity-doped polysilicon, is deposited on the gate insulating layer 14 to form a conductive layer. The conductive layer is patterned via a conventional photolithography process to complete the gate electrode 15. Thereafter, to form LDD region 12c in polysilicon layer 12, an impurity is firstly implanted at a low dosage using gate electrode 15 as an ion-implantation mask. Here, since the impurity is blocked by gate electrode 15, a channel region 12b is formed between the source and drain regions 12a in a portion of the polysilicon layer 12 below gate electrode 15.
Thereafter, the surface portion of gate electrode 15 is thermally oxidized at a high temperature of about 900.degree.-1,000.degree. C. to form a silicon thermal oxide layer 16 on its sidewalls and on the upper surface of gate electrode 15. Thermal oxide layer 16 is formed so as to have a thickness of about 0.1-1.2 .mu.m. Then, a second implantation is performed at a higher dosage by using thermal oxide layer 16 as an ion-implantation mask, to form source and drain regions 12a in the polysilicon layer 12. Therefore, LDD region 12c having a width of about 0.1-1.2 .mu.m is obtained between the source and drain regions 12a and the channel region 12b. On the whole surface of the structure thus obtained, an insulating material such as silicon oxide is deposited to form an insulating interlayer 17. Then, contact holes exposing surface portions of the surface and drain regions 12a and the gate electrode 15 are formed in insulating interlayer 17. Thereafter, metal wirings 18 are formed through the contact holes for electrically connecting the elements of the TFT, to complete a MOS TFT.
In the above described LDD-structured TFT, since the electric field applied between the gate electrode and the drain region is weakened due to the presence of the LDD region, the leakage current may be reduced considerably whenever a reverse bias voltage is applied. The above process exhibits a good reproducibility and may be easily controlled. However, since thermal oxide layer 16 is formed by thermally oxidizing the surface portion of gate electrode 15 at a high temperature of about 1,000.degree. C., the above described TFT cannot be formed on a glass substrate having a process temperature limit of 600.degree. C. When the above TFT should be formed on a glass substrate by a low temperature process, the good crystalline characteristics of the gate electrode may not obtained. Therefore, a higher resistance thereof is obtained than the resistance obtained in the high temperature process. This generates signal delay and increases the line width when forming the TFT having a high packaging density.
FIG. 2 is a sectional view for illustrating a conventional offset-structured MOS TFT for reducing the leakage current.
Referring to FIG. 2, a conventional offset-structured NMOS TFT will be explained hereinafter. On an insulating substrate 20, a polysilicon layer 22 is formed, which comprises an n.sup.+ source and drain regions 22a wherein an n-type impurity has been highly doped, a channel region 22b between source and drain regions 22a and an offset region 22c having a predetermined width between source and drain regions 22a and channel region 22b. On polysilicon layer 22, which comprises source and drain regions 22a, channel region 22b and offset region 22c, an gate insulating layer 24 is formed. A gate electrode 25 comprising a metal is then formed on a portion of the gate insulating layer 24 over channel region 22b. An anodic oxidation layer 26 covering the upper and sidewall surfaces of gate electrode 25 is formed over offset region 22c. Source and drain regions 22a and gate electrode 25 make up an NMOS offset-structured TFT. An insulating interlayer 27 is formed on the structure having the above TFT for electrically isolating the TFT from a conductive layer which is formed in a subsequent step. Metal wirings 28 connected to source and drain regions 22a and gate electrode 25 are then formed on insulating interlayer 27 for operating the abovedescribed TFT.
The above-described NMOS offset-structured TFT is manufactured as follows. A thin polysilicon layer 22 is formed on the insulating substrate 20. On polysilicon layer 22, gate insulating layer 24 is formed by depositing an insulating material such as silicon oxide or by thermally oxidizing the upper surface portion of the polysilicon layer 22. Then, a metal for forming a gate electrode such as aluminum is deposited on gate insulating layer 24 to form a metal layer. The metal layer is patterned via a conventional photolithography process to complete gate electrode 25. Thereafter, the resultant having gate electrode 25 formed thereon is anodic-oxidized via a conventional anodic oxidation to form anodic oxidation layer 26 on its sidewalls and on the upper surface of gate electrode 15. Anodic oxidation layer comprises an oxide of a metal comprising gate electrode 25. Then, ion implantation is performed at a high dosage by using anodic oxidation layer 26 as an ion-implantation mask, to form source and drain regions 22a in the polysilicon layer 22. Consequently, offset region 22c having a predetermined width is obtained between the source and drain regions 22a and the channel region 22b. On the whole surface of the structure thus obtained, an insulating material such as silicon oxide is deposited to form an insulating interlayer 27. Then, contact holes exposing surface portions of the surface and drain regions 22a and the gate electrode 25 are formed in insulating interlayer 27. Thereafter, metal wirings 28 are formed through the contact holes for electrically connecting the elements of the TFT, to complete a MOS TFT.
In the above-described offset-structured TFT, since the electric field applied between the gate electrode and the drain region is weakened due to the presence of the offset region, the leakage current may be reduced considerably whenever a reverse bias voltage is applied. However, for forming a metal wiring 28 to operate gate electrode 25, a contact hole should be formed by partially etching the anodic oxidation layer 26 formed on the gate electrode 25. At this time, since the etching selectivity of anodic oxidation layer 26 with respect to gate electrode 25 is low, there is a high probability that gate electrode 25 would be damaged during the etching step of anodic oxidation layer 26. This deteriorates the reliability of the TFT. Further, anodic oxidation occurs both on the upper and sidewall surfaces of gate electrode 25, the gate electrode should be thicker to increase the thickness of anodic oxidation layer. However, since increasing the thickness of the gate electrode is limited, it is very difficult to obtain an anodic oxidation layer having a desired thickness.